1. Field of the Invention
This invention relates generally to the field of computing systems. More particularly, the invention relates to an improved machine-readable medium and method for warming a CPU to reduce interrupt latency.
2. Description of Related Art
Power management on a data processing system often involves techniques for reducing the consumption of power by components in the data processing system. The data processing system may be a laptop or otherwise portable computer, such as a handheld general purpose computer, a cellular telephone, or a tablet such as iPad. The management of power consumption in a portable device which is powered by a battery is particularly important because better power management usually results in the ability to use the portable device for a longer period of time when it is powered by one or more batteries and for a given duty cycle, in smaller a physical design of the product.
Conventional systems typically utilize timers to indicate when a subsystem should be turned off after a period of inactivity. For example, the motors in a hard drive storage system are typically turned off after a predetermined period of inactivity of the hard drive system. Similarly, the backlight or other light source of a display system may be turned off in response to user inactivity which exceeds a predetermined period of time. In both cases, the power management technique is based on the use of a timer which determines when the period of inactivity exceeds a selected duration.
A typical technique for managing power consumption involves switching operation of a data processing system between different voltage and frequency pairs or “operating points.” In general, a first operating point defined by voltage V1 and operating frequency F1 will consume less power than a second operating point at voltage V2 and operating frequency F2 if V1 is less than V2 and F1 is less than F2.
Certain systems provide the capability to switch power completely off (e.g. set the operating voltage at V=0) if no use is being made of a particular subsystem. For example, certain system-on-a-chip (SOC) systems provide a power gating feature which allows for particular subsystems to be turned off completely if they are not being used.
On some modern microarchitectures, a range of Central Processing Unit (“CPU”) “idle” states are defined to limit energy consumption. These idle states may come with a cost. For urgent tasks (such as real-time or deadline-driven tasks), running at reduced clock speed can cause responsiveness problems or incorrectness. For example, the latency to resume execution can be many microseconds, and its magnitude and unpredictability can pose great challenges to operating systems developers. One important difficulty occurs if the system is concerned with the exact moment that an interrupt is triggered with high precision. With long latencies to exit idle states, it may not be possible to take a timestamp until long after the triggering event.
Additionally, clock speeds may not be adjusted to an optimally low level using current implementations due to “background” tasks which run indefinitely but have no speed requirements. The variety of workloads and unpredictability of CPU load over time make it very difficult to craft a frequency-management algorithm which achieves both responsiveness for high-importance tasks and low power consumption under low-priority load.
Accordingly, what is needed is a more intelligent way to both reduce power consumption and improve responsiveness for certain tasks.